Stack type semiconductor apparatus and system including the stack type semiconductor apparatus

ABSTRACT

A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

CROSS-REFERENCES TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(a) to Koreanapplication No. 10-2016-0014917, filed on Feb. 5, 2016, in the Koreanintellectual property Office, which is incorporated by reference in itsentirety as set forth in full.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor integratedcircuit and/or system, and more particularly, to a stack typesemiconductor apparatus.

2. Related Art

The stack type semiconductor apparatuses may be configured to transfersignals of staked semiconductor chips using through-hole vias.

When the failure of the through-hole via occurs, normal signal transfermay be difficult. Therefore, the repair operation for accuratelydetecting the failed through-hole via and replacing the failedthrough-hole via with a normal through-hole via may be necessary.

SUMMARY

According to an embodiment, there may be provided a stack typesemiconductor apparatus. The stack type semiconductor apparatus mayinclude a plurality of semiconductor chips stacked and configured fortransferring signals through through-hole vias. Each of the plurality ofstacked semiconductor chips may include an error detection circuitconfigured to perform a down scan for transferring a signal to a lowerdirection and an up scan for transferring a signal to an upper directionthrough through-hole vias in a column direction among the through-holevias, and to determine whether the through-hole vias have failedaccording to a down scan result value and an up scan result value.

According to an embodiment, there may be provided a stack typesemiconductor apparatus. The stack type semiconductor apparatus mayinclude a plurality of semiconductor chips stacked and configured fortransferring signals through through-hole vias. Each of the plurality ofstacked semiconductor chips may include an error detection circuitconfigured to perform a down scan by allowing current to flow through athrough-hole via of a lowermost semiconductor chip among the pluralityof semiconductor chips through a through-hole via of an uppermostsemiconductor chip, to perform an up scan by allowing current to flowthrough the through-hole via of the uppermost semiconductor chip fromthe through-hole via of the lowermost semiconductor chip, and todetermine whether the through-hole vias have failed according to a downscan result value and an up scan result value. The stack typesemiconductor apparatus may include a repair circuit configured toswitch an input and output (input/output) (I/O) path coupled to athrough-hole via determined to be a failure through the error detectioncircuit to an I/O path coupled to a normal through-hole via.

According to an embodiment, there may be provided a stack typesemiconductor apparatus. The stack type semiconductor apparatus mayinclude a plurality of semiconductor chips stacked and configured fortransferring signals through through-hole vias. Each of the plurality ofstacked semiconductor chips may include an error detection circuitconfigured to initialize a pre-stored down scan result value accordingto a first preset signal and perform a down scan for transferring asignal to a lower direction through through-hole vias in a columndirection among the through-hole vias, to initialize a pre-stored upscan result value according to a second preset signal and perform an upscan for transferring a signal to an upper direction through thethrough-hole vias in the column direction, and to determine whether thethrough-hole vias have failed according to the down scan result valueand the up scan result value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating a representation of an example of aconfiguration of a semiconductor apparatus according to an embodiment.

FIG. 2 is a view illustrating a representation of an example of aconfiguration of an error detection circuit of FIG. 1.

FIG. 3 is a view illustrating a representation of an example of aconfiguration of a scan control signal generating circuit of FIG. 2.

FIG. 4 is a timing diagram illustrating a representation of an exampleof an operation of the scan control signal generating circuit of FIG. 3.

FIG. 5 is a view illustrating a representation of an example of aconfiguration of a through-hole via scanning circuit of FIG. 2.

FIG. 6 is a view illustrating a representation of an example of aconfiguration of a repair circuit of FIG. 1.

FIG. 7 is a view illustrating a representation of an example of athrough-hole via repair operation according to an embodiment.

FIG. 8 is a view illustrating a representation of an example of aconfiguration of a semiconductor apparatus according to an embodiment.

FIG. 9 is a view illustrating a representation of an example of aconfiguration of an error detection circuit of FIG. 8.

FIG. 10 is a view illustrating a representation of an example of aconfiguration of a scan control signal generating circuit of FIG. 9.

FIG. 11 is a timing diagram illustrating a representation of an exampleof an operation of the scan control signal generating circuit of FIG.10.

FIG. 12 is a view illustrating a representation of an example of aconfiguration of a through-hole via scanning circuit of FIG. 9.

FIG. 13 illustrates a block diagram of an example of a representation ofa system employing a stack type semiconductor apparatus with the variousembodiments discussed above with relation to FIGS. 1-12.

DETAILED DESCRIPTION

One or more examples of embodiments may be provided regarding a stacktype semiconductor apparatus capable of improving accuracy for failuredetection of a through-hole via and a repair operation according to thefailure detection, and reducing a time required for the failuredetection and the repair operation.

Hereinafter, examples of embodiments will be described below withreference to the accompanying drawings. Examples of the embodiments aredescribed herein with reference to cross-sectional illustrations thatare schematic illustrations of examples of the embodiments (andintermediate structures). As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, examples of the embodimentsshould not be construed as limited to the particular shapes of regionsillustrated herein but may be to include deviations in shapes thatresult, for example, from manufacturing. In the drawings, lengths andsizes of layers and regions may be exaggerated for clarity. Likereference numerals in the drawings denote like elements. It is alsounderstood that when a layer is referred to as being “on” another layeror substrate, it can be directly on the other or substrate, orintervening layers may also be present.

The concepts are described herein with reference to cross-section and/orplan illustrations that are schematic illustrations of idealizedembodiments. However, the embodiments should not be limited. Although afew embodiments will be illustrated and described, it will beappreciated by those of ordinary skill in the art that changes may bemade in these examples of embodiments without departing from theprinciples and spirit of the description.

Referring to FIG. 1, a semiconductor apparatus 100 according to anembodiment may include a plurality of stacked semiconductor chips 101 to104.

The plurality of stacked semiconductor chips 101 to 104 may performsignal transfer through through-hole vias, for example, through siliconvias TSV.

The stacked semiconductor chips 101 to 104 may include memory regionsfor information storage and may have the same configuration as eachother.

Each of the stacked semiconductor chips 101 to 104 may include an errordetection circuit 200 and a repair circuit 700.

The error detection circuit 200 may generate failure determinationsignals FAIL<0:n> by detecting a failure of through-hole vias of acorresponding semiconductor chip.

The error detection circuit 200 may perform a down scan for transferringa signal to a lower direction and an up scan for transferring a signalto an upper direction on through-hole vias in a column direction amongthe through-hole vias TSV, and generate the failure determinationsignals FAIL<0:n> by determining whether or not the through-hole viasare failed according to a down scan result value and an up scan resultvalue.

The failure of the through-hole via TSV may refer to a state in whichsignal transfer performance of the through-hole vias is equal to or lessthan a reference value or a state in which signal transfer of thethrough-hole via is impossible.

The repair circuit 700 may replace a through-hole via determined as afailure with a normal through-hole via according to the failuredetermination signals FAIL<0:n>.

The through-hole vias TSV may include spare through-hole vias.

Each of the stacked semiconductor chips 101 to 104 may further includean array fuse circuit 900.

The array fuse circuit 900 may include an array fuse, a logic circuit,and the like configured to input and output information related to acolumn/row repair operation of a failed memory cell among memory cellsin the memory region included in the semiconductor chip.

An operation which inputs, outputs, or inputs/outputs the informationrelated to the column/row repair operation of the failed memory cell inthe array fuse circuit 900 may refer to a boot-up operation. In anembodiment, the error detection circuit 200 may use a signal used in theboot-up operation of the array fuse circuit 900 as the source signalCOUTO.

Referring to FIG. 2, the error detection circuit 200 may include a scancontrol signal generating circuit 300 and a through-hole via scanningcircuit 500.

The scan control signal generating circuit 300 may generate scan controlsignals, that is, an up scan signal UP_SCAN, a down scan signal DN_SCAN,and a latch signal LATCH according to a clock signal CLK and a sourcesignal COUT0.

The clock signal CLK and the source signal COUT0 may be signals whichare to be used in the boot-up operation of the array fuse circuit 900 ofFIG. 1 and may be used in the scan control signal generating circuit500.

The through-hole via scanning circuit 500 may generate a plurality offailure determination signals FAIL<0:n> which define afailure/non-failure of the through-hole vias TSV by performing a scan onthe through-hole vias TSV according to the up scan signal UP_SCAN, thedown scan signal DN_SCAN, and the latch signal LATCH.

The plurality of failure determination signals FAIL<0:n> may define afailure/non-failure of all the through-hole vias TSV, and an example inwhich the number of through-hole vias TSV is n+1 may be described forexample.

First, the through-hole via scanning circuit 500 may generate theplurality of failure determination signals FAIL<0:n> by performing theup scan and down scan for transferring the same signal on thethrough-hole vias TSV in the column direction among the through-holevias TSV.

Referring to FIGS. 3 and 4, the scan control signal generating circuit300 may include a plurality of flip flops FF (i.e., 310) and first toninth logic gates 321, 322, 331, 332, and 341 to 345.

The plurality of flip flops 310 may generate a plurality of shiftsignals COUT1 to COUT7 by sequentially shifting the source signal COUT0according to the clock signal CLK.

The first logic gate 321 may invert the shift signal COUT3 among theplurality of shift signals COUT1 to COUT7 and output an invertingresult.

The second logic gate 322 may perform an AND operation on the sourcesignal COUT0 and an output signal of the first logic gate 321 and outputan AND operation result as the down scan signal DN_SCAN.

The third logic gate 331 may invert the shift signal COUT6 among theplurality of shift signals COUT1 to COUT7 and output an invertingresult.

The fourth logic gate 332 may perform an AND operation on the shiftsignal COUT3 among the plurality of shift signals COUT1 to COUT7 and anoutput signal of the third logic gate 331 and output an AND operationresult as the up scan signal UP_SCAN.

The fifth logic gate 341 may invert the shift signal COUT2 among theplurality of shift signals COUT1 to COUT7 and output an invertingresult.

The sixth logic gate 342 may perform an NAND operation on the shiftsignal COUT1 among the plurality of shift signals COUT1 to COUT7 and anoutput signal of the fifth logic gate 341 and output a NAND operationresult.

The seventh logic gate 343 may invert the shift signal COUT5 among theplurality of shift signals COUT1 to COUT7 and output an invertingresult.

The eighth logic gate 344 may perform an NAND operation on the shiftsignal COUT4 among the plurality of shift signals COUT1 to COUT7 and anoutput signal of the seventh logic gate 343 and output an NAND operationresult.

The ninth logic gate 345 may perform an NAND operation on an outputsignal of the sixth logic gate 342 and an output signal of the eighthlogic gate 344 and output an NAND operation result as the latch signalLATCH.

Referring to FIG. 4, the down scan signal DN_SCAN may be activatedduring a periodf from a rising edge of the source signal COUT0 to arising edge of the shift signal COUT3, and then the up scan signalUP_SCAN may be activated during a period from the rising edge of theshift signal COUT3 to a rising edge of the shift signal COUT6.

The latch signal LATCH may be activated once in the activation period ofthe down scan signal DN_SCAN and once in the activation period of the upscan signal UP_SCAN.

Referring to FIG. 5, the through-hole via scanning circuit 500 may beincluded in each of the stacked semiconductor chips 101 to 104. FIG. 5illustrates an example of the through-hole via scanning circuits 500corresponding to through-hole vias which are included in the stackedsemiconductor chips 101 to 104 one by one and arranged on the same linein the column direction among the through-hole vias TSV of the stackedsemiconductor chips 101 to 104.

The through-hole via scanning circuit 500 may include a current source510, a current leaker 520, and a failure determination circuit 530.

The current source 510 may allow current to flow to the through-hole viaTSV from a power terminal according to the up scan signal UP_SCAN or thedown scan signal DOWN_SCAN, and may include an inverter and a PMOStransistor.

The current leaker 520 may allow current to flow to a ground terminalfrom the through-hole via TSV according to the up scan signal UP_SCAN ordown scan signal DN_SCAN, and may include an NMOS transistor.

The failure determination circuit 530 may generate the plurality offailure determination signals FAIL<0:n> based on voltage levels of thethrough-hole vias TSV according to the up scan signal UP_SCAN and thedown scan signal DN_SCAN.

The failure determination circuit 530 may include first to seventh logicgates 531 to 537 and first and second latches 538 and 539.

The first logic gate 531 may perform an AND operation on the down scansignal DN_SCAN and the latch signal LATCH and output an AND operationresult.

The second logic gate 532 may invert an output signal of the first logicgate 531 and output an inverting result.

The third logic gate 533 may receive the output signal of the firstlogic gate 531 through a non-inverting control terminal and receive anoutput signal of the second logic gate 532 through an inverting controlterminal.

The third logic gate 533 may transmit an input signal only when a levelof the non-inverting control terminal is logic high and a level of theinverting control terminal is logic low.

The first latch 538 may latch an output signal of the third logic gate533.

The fourth logic gate 534 may perform an AND operation on the up scansignal UP_SCAN and the latch signal LATCH and output an AND operationresult.

The fifth logic gate 535 may invert an output signal of the fourth logicgate 534 and output an inverting result.

The sixth logic gate 536 may receive the output signal of the fourthlogic gate 534 through a non-inverting control terminal and receive anoutput signal of the fifth logic gate 535 through an inverting controlterminal.

The sixth logic gate 536 may transmit an input signal only when a levelof the non-inverting control terminal is logic high and a level of theinverting control terminal is logic low.

The second latch 539 may latch an output signal of the sixth logic gate536.

The seventh logic gate 537 may perform an NAND operation on a signallatched in the first latch 538 and a signal latched in the second latch539 and output an NAND operation result as one of the plurality offailure determination signals FAIL<0:n> corresponding to correspondingone among the through-hole vias of the semiconductor chip.

The down scan signal DN_SCAN may be input to the current source 510 ofthe uppermost semiconductor chip 104 among the stacked semiconductorchips 101 to 104 and the up scan signal UP_SCAN may be input to thecurrent leaker 520 of the uppermost semiconductor chip 104.

The up scan signal UP_SCAN may be input to the current source 510 of thelowermost semiconductor chip 101 among the stacked semiconductor chips101 to 104 and the down scan signal DN_SCAN may be input to the currentleaker 520 of the lowermost semiconductor chip 101.

Input terminals of the current sources 510 and the current leakers 520of other semiconductor chips 102 and 103 other than the uppermostsemiconductor chip 104 and the lowermost semiconductor chip 101, thatis, input terminals of the inverters and gates of the NMOS transistorsin the other semiconductor chips 102 and 103 may be floating.

Stacking information according to the stacking of the semiconductorchips 101 to 104 may be stored in each of the stacked semiconductorchips 101 to 104.

The stacking information may be information which defines a stakedposition of a corresponding semiconductor chip, that is, an uppermostposition, a lowermost position, or a middle position.

According to the stack type semiconductor apparatus according to anembodiment, the through-hole via scanning circuit 500 may selectivelyinput the down scan signal DN_SCAN and the up scan signal UP_SCAN to thecurrent source 510 and the current leaker 520 or allow the currentsource 510 and the current leaker 520 to be floating, according to thestacked position of a corresponding semiconductor chip among the stackedsemiconductor chips using the stacking information as illustrated inFIG. 5.

The through-hole via failure detection operation according to anembodiment will be described with reference to FIGS. 4 and 5.

First, as the down scan signal DN_SCAN is activated, current may flowfrom the current source 510 of the uppermost semiconductor chip 104 tothe current leaker 520 of the lowermost semiconductor chip 101 throughthe through-hole vias TSV.

Since the up scan signal UP_SCAN is inactivated during the activationperiod of the down scan signal DN_SCAN, the current leaker 520 of theuppermost semiconductor chip 104 and the current source 510 of thelowermost semiconductor chip 101 may be inactivated.

As the latch signal LATCH is activated in a state that the down scansignal DN_SCAN is activated, the failure determination circuit 530 ineach of the stacked semiconductor chips 101 to 104 may store a voltagelevel according to the current flowing through the through-hole via TSVcoupled to the corresponding failure determination circuit 530 as thedown scan result value.

Subsequently, as the up scan signal UP_SCAN is activated, current mayflow from the current source 510 of the lowermost semiconductor chip 101to the current leaker 520 of the uppermost semiconductor chip 104through the through-hole vias TSV.

Since the down scan signal DN_SCAN is inactivated during the activationperiod of the up scan signal UP_SCAN, the current leaker 520 of thelowermost semiconductor chip 101 and the current source 510 of theuppermost semiconductor chip 104 may be inactivated.

As the latch signal LATCH is activated in a state that the up scansignal UP_SCAN is activated, the failure determination circuit 530 ineach of the stacked semiconductor chips 101 to 104 may store a voltagelevel according to the current flowing through the through-hole via TSVcoupled to the corresponding failure determination circuit 530 as the upscan result value.

The failure determination circuit 530 in each of the stackedsemiconductor chips 101 to 104 may inactivate corresponding one of thefailure determination signals FAIL<0:n> to a low level when both thestored down scan result value and the stored up scan result value have avalue (for example, a high level) which defines a normal state of thecorresponding through-hole via TSV.

The failure determination circuit 530 may activate the corresponding oneof the failure determination signals FAIL<0:n> to a high level when anyone of the stored down scan result value and the stored up scan resultvalue has a value (for example, a low level) which defines a failure ofthe corresponding through-hole via TSV.

FIG. 6 illustrates the repair circuit 700 for partial through-hole viasTSV<m:m+2> among the through-hole vias TSV.

Referring to FIG. 6, the repair circuit 700 may include first I/Odrivers 710 to 712 and second I/O drivers 720 to 722 coupled to thethrough-hole vias TSV<m:m+2>.

The first I/O drivers 710 to 712 may have the same configuration as eachother, and the second I/O drivers 720 to 722 may have the sameconfiguration as each other.

The first I/O drivers 710 to 712 and the second I/O drivers 720 to 722may be configured to switch an I/O path coupled to a failed through-holevia TSV to an I/O path coupled to a normal through-hole via TSVaccording to the failure determination signals FAIL<m:m+2>.

The first I/O driver 710 may be coupled between first signal I/O linesGIO<m−1> and GIO<m> among first signal I/O lines GIO<m−1:m+2> andthrough-hole vias TSV<m> and TSV<m+1> among the through-hole viasTSV<m:m+2>.

The first I/O driver 710 may include an input driver RX and an outputdriver TX.

The input driver RX of the first I/O driver 710 may drive a signaltransferred through the first signal I/O line GIO<m> or a previous firstsignal I/O line GIO<m−1> to the through-hole via TSVm according to afailure determination signal FAIL<m>.

The output driver TX of the first I/O driver 710 may drive a signaltransferred through the through-hole via TSV<m> or next through-hole viaTSV<m+1> to the first signal I/O line GIO<m> according to the failuredetermination signal FAIL<m>.

The second I/O driver 720 may be coupled between through-hole viasTSV<m> and TSV<m+1> among the through-hole vias TSV<m:m+2> and secondsignal I/O lines MIO<m−1> and MIO<m> among the second signal I/O linesMIO<m−1:m+2>.

The second I/O driver 720 may include an input driver RX and an outputdriver TX.

The input driver RX of the second I/O driver 720 may drive a signaltransferred through the second signal I/O line MIO<m> or a previoussecond signal I/O line MIO<m−1> to the through-hole via TSV<m> accordingto the failure determination signal FAIL<m>.

The output driver TX of the second I/O driver 720 may drive a signaltransferred through the through-hole via TSV<m> or next through-hole viaTSV<m+1> to the second signal I/O line MIO<m> according to the failuredetermination signal FAIL<m>.

A repair operation for the through-hole via TSV according to anembodiment will be described with reference to FIG. 7.

For example, the repair operation when the through-hole via TSV<m+1>among the through-hole vias TSV is failed will be described.

Since the through-hole via TSV<m+1> is failed, the failure determinationsignal FAIL<m+1> among the failure determination signals FAIL<m:m+2> mayhave been activated through the through-hole via failure detectionoperation which has been already described with reference to FIGS. 4 and5, and next failure determination signals including the failuredetermination signal FAIL<m+2> may also be activated.

The repair operation for the through-hole via TSV according to anembodiment may be performed through a method which shifts the I/O pathcoupled to the failed through-hole via TSV, that is, a method whichcouples the I/O path coupled to the failed through-hole via TSV to theright normal through-hole via TSV on the basis of FIG. 7.

When the failure determination signal FAIL<m+1> is activated, failuredetermination signals including the failure determination signalFAIL<m+2> next to the failure determination signal FAIL<m+1> may also beactivated.

Since the failure determination signal FAIL<m> is in an inactivationstate, signal I/O between the first signal I/O line GIO<m> and thesecond signal I/O line MIO<m> may be performed through the through-holevia TSV<m> by the first I/O driver 710 and the second I/O driver 720.

Since the failure determination signal FAIL<m+1> is in an activationstate, signal I/O between the first signal I/O line GIO<m+1> and thesecond signal I/O line MIO<m+1> may be performed through thethrough-hole via TSV<m+2> by the first I/O drivers 711 and 712 and thesecond I/O drivers 721 and 722.

As described above, the repair operation may be accomplished by shiftingthe signal I/O path between the first signal I/O lines GIO and thesecond signal I/O lines MIO to the right through-hole via TSV<m+2> byone on the basis of the failed through-hole via TSV<m+1>.

Referring to FIG. 8, a semiconductor apparatus 1000 according to anembodiment may include a plurality of stacked semiconductor chips 101 to104.

Each of the stacked semiconductor chips 101 to 104 may include an errordetection circuit 201 and a repair circuit 700.

The error detection circuit 201 may generate failure determinationsignals FAIL<0:n> by detecting a failure of through-hole vias TSV of acorresponding semiconductor chip.

The error detection circuit 201 may initialize a pre-stored down scanresult value and perform down scan for transferring a signal to a lowerdirection on through-hole vias in a column direction among thethrough-hole vias TSV, may initialize a pre-stored up scan result valueand perform up scan for transferring a signal to an upper direction onthe through-hole vias in the column direction, and may generate thefailure determination signals FAIL<0:n> by determining whether or notthe through-hole vias TSV are failed according to a down scan resultvalue and an up scan result value.

The repair circuit 700 may replace a through-hole via determined as afailure according to the failure determination signals FAIL<0:n> with anormal through-hole via.

The configuration and operation of the repair circuit 700 may be thesame as those of the repair circuit 700 of FIG. 1 described withreference to FIGS. 6 and 7, and thus a detailed description thereof willbe omitted.

Each of the stacked semiconductor chips 101 to 104 may further includean array fuse circuit 900.

The array fuse circuit 900 may include an array fuse, a logic circuit,and the like configured to input and output information related to acolumn/row repair operation of a failed memory cell among memory cellsin a memory region included in the semiconductor chip.

Referring to FIG. 9, the error detection circuit 201 may include a scancontrol signal generating circuit 301 and a through-hole via scanningcircuit 501.

The scan control signal generating circuit 301 may generate scan controlsignals, that is, a first preset signal PRESET_DN, a down scan signalDN_SCAN, a second preset signal PRESET_UP, and an up scan signal UP_SCANaccording to a boot-up count signal BU_CNT.

The boot-up count signal BU_CNT may be a signal used in a boot-upoperation of the array fuse circuit 900 of FIG. 8.

The through-hole via scanning circuit 501 may perform initialization fora pre-stored down scale result value, initialization for a pre-stored upscan result value, down scan, and up scan according to the first presetsignal PRESET_DN, the down scan signal DN_SCAN, the second preset signalPRESET_UP, and the up scan signal UP_SCAN and generate a plurality offailure determination signals FAIL<0:n> which define afailure/non-failure of the through-hole vias according to the down scanresult value and the up scan result value.

The plurality of failure determination signals FAIL<0:n> may define thefailure/non-failure of all the through-hole vias TSV, and an example inwhich the number of through-hole vias TSV is n+1 may be described forexample.

First, the through-hole via scanning circuit 501 may generate theplurality of failure determination signals FAIL<0:n> by performing theup scan and down scan for transferring the same signal on through-holevias TSV in the column direction among the through-hole vias TSV.

Referring to FIG. 10, the scan control signal generating circuit 301 mayinclude a flip-flop array 350 and a counter 360.

Flip-flops 351 of the flip-flop array 350 may generate the scan controlsignals, that is, the first preset signal PRESET_DN, the down scansignal DN_SCAN, the second preset signal PRESET_UP, and the up scansignal UP_SCAN by sequentially shifting a scan start signal SCAN_STARTaccording to the boot-up count signal BU_CNT.

The counter 360 may activate the scan start signal SCAN_START at apreset timing by counting the boot-up count signal BU_CNT.

Referring to FIG. 11, the first preset signal PRESET_DN may be activatedin response to next boot-up count signal BU_CNT immediately after thescan start signal SCAN_START is activated, and the down scan signalDN_SCAN, the second preset signal PRESET_UP, and the up scan signalUP_SCAN may be sequentially activated at fixed intervals on the basis ofa pulse of the boot-up count signal BU_CNT.

The timing diagram of FIG. 11 is exemplified only on the basis of thecircuit configuration of the through-hole via scanning circuit 301 ofFIG. 10, and the first preset signal PRESET_DN, the down scan signalDN_SCAN, the second preset signal PRESET_UP, and the up scan signalUP_SCAN may be activated at a desired timing and at desired intervals byadjusting an inner setup value of the counter 360 or by adjustingflip-flops 351 for withdrawal of output signals among the flip flops351.

Referring to FIG. 12, the through-hole via scanning circuit 501 may beincluded in each of the stacked semiconductor chips 101 to 104. FIG. 12illustrates an example of the through-hole via scanning circuits 501corresponding to through-hole vias which are included in the stackedsemiconductor chips 101 to 104 one by one and arranged on the same linein the column direction among the through-hole vias TSV of the stackedsemiconductor chips 101 to 104.

The through-hole via scanning circuit 501 may include a current source510, a current leaker 520, and a failure determination circuit 540.

The current source 510 and the current leaker 520 may have the sameconfigurations as those in the through-hole via scanning circuit 500 ofFIG. 5.

The failure determination circuit 540 may initialize a pre-stored downscan result value according to the first preset signal PRESET_DN andnewly store the down scan result value according to the down scan signalDN_SCAN.

The failure determination circuit 540 may initialize a pre-stored upscan result value according to the second preset signal PRESET_UP andnewly store the up scan result value according to the up scan signalUP_SCAN.

The failure determination circuit 540 may generate the plurality offailure determination signals FAIL<0:n> by combining the newly storeddown scan result value and the newly stored up scan result value.

The failure determination result 540 may store voltage levels of thethrough-hole vias according to the up scan signal UP_SCAN and the downscan signal DN_SCAN as the down scan result value and the up scan resultvalue.

The failure determination circuit 540 may include a first pass gate(PG1) 541, a second pass gate (PG2) 542, a first latch 543, a secondlatch 544, a logic gate, for example, a NAND gate 545, a firsttransistor 546, and a second transistor 547.

The first pass gate 541 may store an input signal, that is, a voltagelevel of the through-hole via TSV in the first latch 543 when the downscan signal DN_SCAN is a high level.

The second pass gate 542 may store an input signal, that is, a voltagelevel of the through-hole via TSV in the second latch 544 when the upscan signal UP_SCAN is a high level.

The NAND gate 545 may output a corresponding failure determinationsignal of a low level among the failure determination signals FAIL<0:n>when both the signal levels stored in the first latch 543 and the secondlatch 544 are a high level, and output the corresponding failuredetermination signal of a high level among the failure determinationsignals FAIL<0:n> when any one of the signal levels stored in the firstand second latches 543 and 544 is a low level.

The first transistor 546 may initialize the pre-stored down scan resultvalue, that is, the signal level pre-stored in the first latch 543 to ahigh level when the first preset signal PRESET_DN is a high level.

The second transistor 547 may initialize the pre-stored up scan resultvalue, that is, the signal level pre-stored in the second latch 544 to ahigh level when the second preset signal PRESET_UP is a high level.

Since both the signal level stored in the first latch 543 and the signallevel stored in the second latch 544 are the high level, thecorresponding failure determination signal among the failuredetermination signals FAIL<0:n> may be initialized to the low level.

The down scan signal DN_SCAN may be input to the current source 510 ofthe uppermost semiconductor chip 104 among the stacked semiconductorchips 101 to 104, and the up scan signal UP_SCAN may be input to thecurrent leaker 520 of the uppermost semiconductor chip 104.

The up scan signal UP_SCAN may be input to the current source 510 of thelowermost semiconductor chip 101 among the stacked semiconductor chips101 to 104 and the down scan signal DN_SCAN may be input to the currentleaker 520 of the lowermost semiconductor chip 101.

Input terminals of the current sources 510 and the current leakers 520of other semiconductor chips 102 and 103 other than the uppermostsemiconductor chip 104 and the lowermost semiconductor chip 101, thatis, input terminals of inverters and gates of NMOS transistors in theother semiconductor chips 102 and 103 may be floating.

Stacking information according to stacked positions of the semiconductorchips 101 to 104 may be stored in each of the stacked semiconductorchips 101 to 104.

The stacking information may be information which defines a stakedposition of a corresponding semiconductor chip, that is, an uppermostposition, a lowermost position, or a middle position.

According to the stack type semiconductor apparatus according to anembodiment, the through-hole via scanning circuit 501 may selectivelyinput the down scan signal DN_SCAN and the up scan signal UP_SCAN to thecurrent source 510 and the current leaker 520 or allow the currentsource 510 and the current leaker 520 to be floating, according to thestacked position of a corresponding semiconductor chip among the stackedsemiconductor chips using the stacking information as illustrated inFIG. 12.

The through-hole via failure detection operation according to anembodiment will be described with reference to FIGS. 11 and 12.

An abnormal signal related to the scan operation before a boot-upoperation may be generated due to several reasons after the power-up ofthe semiconductor apparatus.

Then, the boot-up operation may be performed and the boot-up countsignal BU_CNT may be activated according to the boot-up operation.

The scan start signal SCAN_START may be activated at a preset timingafter pulses of the boot-up count signal BU_CNT may be generated, andthe first preset signal PRESET_DN, and the down scan signal DN_SCAN, thesecond preset signal PRESET_UP, and the up scan signal UP_SCAN may besequentially activated according to the scan start signal SCAN_START.

The pre-stored down scan result value may be initialized to the highlevel according to the first preset signal PRESET_DN.

As the down scan signal DN_SCAN is activated, current may flow from thecurrent source 510 of the uppermost semiconductor chop 104 to thecurrent leaker 520 of the lowermost semiconductor chip 101 throughthrough-hole vias TSV.

Since the up scan signal UP_SCAN is inactivated during the activationperiod of the down scan signal DN_SCAN, the current leaker 520 of theuppermost semiconductor chip 104 and the current source 510 of thelowermost semiconductor chip 101 may be inactivated.

As the down scan signal DN_SCAN is activated, the failure determinationcircuit 540 in each of the stacked semiconductor chips 101 to 104 maynewly store a voltage level according to the current flowing through athrough-hole via TSV coupled to the corresponding failure determinationcircuit 540 as the down scan result value.

The pre-stored up scan result value may be initialized to the high levelaccording to the second preset signal PRESET_UP.

Subsequently, as the up scan signal UP_SCAN is activated, current mayflow from the current source 510 of the lowermost semiconductor chip 101to the current leaker 520 of the uppermost semiconductor chip 104through the through-hole vias TSV.

Since the down scan signal DN_SCAN is inactivated during the activationperiod of the up scan signal UP_SCAN, the current leaker 520 of thelowermost semiconductor chip 101 and the current source 510 of theuppermost semiconductor chip 104 may be inactivated.

As the up scan signal UP_SCAN is activated, the failure determinationcircuit 540 in each of the stacked semiconductor chips 101 to 104 maynewly store a voltage level according to the current flowing through thethrough-hole via TSV coupled to the corresponding failure determinationcircuit 540 as the up scan result value.

When both the newly stored down scan result value and the newly storedup scan result value are a high level which defines a normal state ofthe corresponding through-hole via TSV, the failure determinationcircuit 540 in each of the stacked semiconductor chips 101 to 104 mayoutput a corresponding failure determination signal of a low level amongthe failure determination signals FAIL<0:n>.

When any one of the newly stored down scan result value and the newlystored up scan result value is a low level which defines a failure ofthe corresponding through-hole via TSV, the failure determinationcircuit may output the corresponding failure determination signal of ahigh level among the failure determination signals FAIL<0:n>.

The stack type semiconductor apparatuses as discussed above (see FIGS.1-12) are particular useful in the design of memory devices, processors,and computer systems. For example, referring to FIG. 13, a block diagramof a system employing a stack type semiconductor apparatus in accordancewith the various embodiments are illustrated and generally designated bya reference numeral 1000. The system 1000 may include one or moreprocessors (i.e., Processor) or, for example but not limited to, centralprocessing units (“CPUs”) 1100. The processor (i.e., CPU) 1100 may beused individually or in combination with other processors (i.e., CPUs).While the processor (i.e., CPU) 1100 will be referred to primarily inthe singular, it will be understood by those skilled in the art that asystem 1000 with any number of physical or logical processors (i.e.,CPUs) may be implemented.

A chipset 1150 may be operably coupled to the processor (i.e., CPU)1100. The chipset 1150 is a communication pathway for signals betweenthe processor (i.e., CPU) 1100 and other components of the system 1000.Other components of the system 1000 may include a memory controller1200, an input/output (“I/O”) bus 1250, and a disk driver controller1300. Depending on the configuration of the system 1000, any one of anumber of different signals may be transmitted through the chipset 1150,and those skilled in the art will appreciate that the routing of thesignals throughout the system 1000 can be readily adjusted withoutchanging the underlying nature of the system 1000.

As stated above, the memory controller 1200 may be operably coupled tothe chipset 1150. The memory controller 1200 may include at least onestack type semiconductor apparatus as discussed above with reference toFIGS. 1-12. Thus, the memory controller 1200 can receive a requestprovided from the processor (i.e., CPU) 1100, through the chipset 1150.In alternate embodiments, the memory controller 1200 may be integratedinto the chipset 1150. The memory controller 1200 may be operablycoupled to one or more memory devices 1350. In an embodiment, the memorydevices 1350 may include the at least one stack type semiconductorapparatus as discussed above with relation to FIGS. 1-12, the memorydevices 1350 may include a plurality of word lines and a plurality ofbit lines for defining a plurality of memory cells. The memory devices1350 may be any one of a number of industry standard memory types,including but not limited to, single inline memory modules (“SIMMs”) anddual inline memory modules (“DIMMs”). Further, the memory devices 1350may facilitate the safe removal of the external data storage devices bystoring both instructions and data.

The chipset 1150 may also be coupled to the I/O bus 1250. The I/O bus1250 may serve as a communication pathway for signals from the chipset1150 to I/O devices 1410, 1420, and 1430. The I/O devices 1410, 1420,and 1430 may include, for example but are not limited to, a mouse 1410,a video display 1420, or a keyboard 1430. The I/O bus 1250 may employany one of a number of communications protocols to communicate with theI/O devices 1410, 1420, and 1430. In an embodiment, the I/O bus 1250 maybe integrated into the chipset 1150.

The disk driver controller 1300 may be operably coupled to the chipset1150. The disk driver controller 1300 may serve as the communicationpathway between the chipset 1150 and one internal disk driver 1450 ormore than one internal disk driver 1450. The internal disk driver 1450may facilitate disconnection of the external data storage devices bystoring both instructions and data. The disk driver controller 1300 andthe internal disk driver 1450 may communicate with each other or withthe chipset 1150 using virtually any type of communication protocol,including, for example but not limited to, all of those mentioned abovewith regard to the I/O bus 1250.

It is important to note that the system 1000 described above in relationto FIG. 13 is merely one example of a system 1000 employing a stack typesemiconductor apparatus as discussed above with relation to FIGS. 1-12.In alternate embodiments, such as, for example but not limited to,cellular phones or digital cameras, the components may differ from theembodiments illustrated in FIG. 13.

The above embodiments of the description are illustrative and notlimitative. Various alternatives and equivalents are possible. Thedescription is not limited by the embodiments described herein. Nor arethe embodiments limited to any specific type of semiconductor device.Other additions, subtractions, or modifications are obvious in view ofthe present disclosure and are intended to fall within the scope of theappended claims.

What is claimed is:
 1. A stack type semiconductor apparatus comprising:a plurality of semiconductor chips stacked and configured fortransferring signals through through-hole vias, wherein each of theplurality of stacked semiconductor chips includes an error detectioncircuit configured to perform a down scan for transferring a signal to alower direction and an up scan for transferring a signal to an upperdirection through through-hole vias in a column direction among thethrough-hole vias, and to determine whether the through-hole vias havefailed according to a down scan result value and an up scan resultvalue.
 2. The stack type semiconductor apparatus of claim 1, wherein theerror detection circuit is configured to perform the down scan byallowing current to flow to the lower direction through the through-holevias in the column direction and perform the up scan by allowing currentto flow to the upper direction through the through-hole vias in thecolumn direction.
 3. The stack type semiconductor apparatus of claim 1,wherein the error detection circuit includes: a scan control signalgenerating circuit configured to generate scan control signals accordingto a source signal; and a through-hole via scanning circuit configuredto generate failure determination signals which define a failure ornon-failure of the through-hole vias by performing the down scan and theup scan according to the scan control signals.
 4. The stack typesemiconductor apparatus of claim 3, wherein each of the plurality ofsemiconductor chips further includes an array fuse circuit configured tostore information of a memory cell determined to be a failure, and theerror detection circuit uses a signal used in a boot-up operation of thearray fuse circuit as the source signal.
 5. The stack type semiconductorapparatus of claim 3, wherein the scan control signal generating circuitis configured to generate a plurality of shift signals by sequentiallyshifting the source signal according to a clock signal, and generate thescan control signals by combining the plurality of shift signals inpreset circuits.
 6. The stack type semiconductor apparatus of claim 3,wherein the through-hole via scanning circuit includes: a current sourceconfigured to allow current to flow from a power terminal to athrough-hole via among the through-hole vias according to a down scansignal or an up scan signal; a current leaker configured to allowcurrent to flow from the through-hole via to a ground terminal accordingto the up scan signal or the down scan signal; and a failuredetermination circuit configured to generate a failure determinationsignal corresponding to the through-hole via according to voltage levelsof the through-hole via according to the up scan signal and the downscan signal.
 7. The stack type semiconductor apparatus of claim 6,wherein the failure determination circuit is configured to store thedown scan result value according to the down scan signal and a latchsignal, store the up scan result value according to the up scan signaland the latch signal, and generate the failure determination signal bycombining the down scan result value and the up scan result value. 8.The stack type semiconductor apparatus of claim 6, wherein each of theplurality of semiconductor chips is configured to store stackinginformation which defines its corresponding stacked position relative toother semiconductor chips within the plurality of semiconductor chipsstacked, and the through-hole via scanning circuit is configured toselectively provide the up scan signal or the down scan signal to thecurrent source according to the stacking information.
 9. The stack typesemiconductor apparatus of claim 6, wherein each of the plurality ofsemiconductor chips is configured to store stacking information whichdefines its own stacked position, and the through-hole via scanningcircuit is configured to allow current sources of other semiconductorchips other than an uppermost semiconductor chip and a lowermostsemiconductor chip among the plurality of semiconductor chips to befloating according to the stacking information.
 10. The stack typesemiconductor apparatus of claim 1, wherein the error detection circuitis configured to perform the down scan by allowing current to flow to athrough-hole via of a lowermost semiconductor chip among thesemiconductor chips through a through-hole via of an uppermostsemiconductor chip and perform the up scan by allowing current to flowto the through-hole via of the uppermost semiconductor chip from thethrough-hole via of the lowermost semiconductor chip.
 11. A stack typesemiconductor apparatus comprising: a plurality of semiconductor chipsstacked and configured for transferring signals through through-holevias, wherein each of the plurality of semiconductor chips includes: anerror detection circuit configured to perform a down scan by allowingcurrent to flow through a through-hole via of a lowermost semiconductorchip among the plurality of semiconductor chips through a through-holevia of an uppermost semiconductor chip, to perform an up scan byallowing current to flow through the through-hole via of the uppermostsemiconductor chip from the through-hole via of the lowermostsemiconductor chip, and to determine whether the through-hole vias havefailed according to a down scan result value and an up scan resultvalue; and a repair circuit configured to switch an input and output(I/O) path coupled to a through-hole via determined to be a failurethrough the error detection circuit to an I/O path coupled to a normalthrough-hole via.
 12. The stack type semiconductor apparatus of claim11, wherein the error detection circuit includes: a scan control signalgenerating circuit configured to generate scan control signals accordingto a source signal; and a through-hole via scanning circuit configuredto generate failure determination signals which define a failure ornon-failure of the through-hole vias by performing the down scan and theup scan according to the scan control signals.
 13. The stack typesemiconductor apparatus of claim 12, wherein each of the plurality ofsemiconductor chips further includes an array fuse circuit configured tostore information of a memory cell determined to be a failure, and theerror detection circuit uses a signal used in a boot-up operation of thearray fuse circuit as the source signal.
 14. The stack typesemiconductor apparatus of claim 12, wherein the scan control signalgenerating circuit is configured to generate a plurality of shiftsignals by sequentially shifting the source signal according to a clocksignal, and generate the scan control signals by combining the pluralityof shift signals in preset circuits.
 15. The stack type semiconductorapparatus of claim 12, wherein the through-hole via scanning circuitincludes: a current source configured to allow current to flow from apower terminal to a through-hole via among the through-hole viasaccording to a down scan signal or an up scan signal; a current leakerconfigured to allow current to flow from the through-hole via to aground terminal according to the up scan signal or the down scan signal;and a failure determination circuit configured to generate a failuredetermination signal corresponding to the through-hole via according tovoltage levels of the through-hole via according to the up scan signaland the down scan signal.
 16. The stack type semiconductor apparatus ofclaim 15, wherein the failure determination circuit is configured tostore the down scan result value according to the down scan signal and alatch signal, store the up scan result value according to the up scansignal and the latch signal, and generate the failure determinationsignal by combining the down scan result value and the up scan resultvalue.
 17. The stack type semiconductor apparatus of claim 15, whereineach of the plurality of semiconductor chips is configured to storestacking information which defines its corresponding stacked positionrelative to other semiconductor chips within the plurality ofsemiconductor chips stacked, and the through-hole via scanning circuitis configured to selectively provide the up scan signal or the down scansignal to the current source according to the stacking information. 18.The stack type semiconductor apparatus of claim 15, wherein each of theplurality of semiconductor chips is configured to store stackinginformation which defines its own stacked position, and the through-holevia scanning circuit is configured to allow current sources of othersemiconductor chips other than an uppermost semiconductor chip and alowermost semiconductor chip among the plurality of semiconductor chipsto be floating according to the stacking information.
 19. The stack typesemiconductor apparatus of claim 11, wherein the repair circuitincludes: a first input driver configured to drive a signal transferredthrough a first line or a second line among first signal I/O lines to afirst through-hole via among the through-hole vias according to afailure determination signal; and a first output driver configured todrive a signal transferred through the first through-hole via or asecond through-hole via to the first line according to the failuredetermination signal.
 20. A stack type semiconductor apparatuscomprising: a plurality of semiconductor chips stacked and configuredfor transferring signals through through-hole vias, wherein each of theplurality of stacked semiconductor chips includes an error detectioncircuit configured to initialize a pre-stored down scan result valueaccording to a first preset signal and perform a down scan fortransferring a signal to a lower direction through through-hole vias ina column direction among the through-hole vias, to initialize apre-stored up scan result value according to a second preset signal andperform an up scan for transferring a signal to an upper directionthrough the through-hole vias in the column direction, and to determinewhether the through-hole vias have failed according to a down scanresult value and an up scan result value.
 21. The stack typesemiconductor apparatus of claim 20, wherein the error detection circuitincludes: a scan control signal generating circuit configured togenerate the preset signal, a down scan signal, the second presetsignal, and an up scan signal according to a boot-up count signal; and athrough-hole via scanning circuit configured to perform the down scanand the up scan according to the first preset signal, the down scansignal, the second preset signal, and the up scan signal, and generatefailure determination signals which define a failure or non-failure ofthe through-hole vias according to the down scan result value and the upscan result value.
 22. The stack type semiconductor apparatus of claim21, wherein each of the plurality of semiconductor chips furtherincludes an array fuse circuit configured to store information for amemory cell determined to be a failure, and the boot-up count signal isused in a boot-up operation of the array fuse circuit.
 23. The stacktype semiconductor apparatus of claim 21, wherein the scan controlsignal generating circuit includes: a flip-flop array configured togenerate the first preset signal, the down scan signal, the secondpreset signal, and the up scan signal by sequentially shifting a scanstart signal according to the boot-up count signal; and a counterconfigured to generate the scan start signal according to the boot-upcount signal.
 24. The stack type semiconductor apparatus of claim 21,wherein the through-hole via scanning circuit includes: a current sourceconfigured to allow current to flow from a power terminal to athrough-hole via among the through-hole vias according to the down scansignal or the up scan signal; a current leaker configured to allowcurrent to flow from the through-hole via to a ground terminal accordingto the up scan signal or the down scan signal; and a failuredetermination circuit configured to generate a failure determinationsignal corresponding to the through-hole via according to voltage levelsof the through-hole via according to the up scan signal and the downscan signal.
 25. The stack type semiconductor apparatus of claim 24,wherein the failure determination circuit is configured to initializethe pre-stored down scan result value according to the first presetsignal and newly store the down scan result value according to the downscan signal, to initialize the pre-stored up scan result value accordingto the second preset value and newly store the up scan result valueaccording to the up scan signal, and to generate the failuredetermination signal by combining the down scan result value and the upscan result value.
 26. The stack type semiconductor apparatus of claim24, wherein each of the plurality of semiconductor chips is configuredto store stacking information which defines its corresponding stackedposition relative to other semiconductor chips within the plurality ofsemiconductor chips stacked, and the through-hole via scanning circuitis configured to selectively provide the up scan signal or the down scansignal to the current source according to the stacking information. 27.The stack type semiconductor apparatus of claim 24, wherein each of theplurality of semiconductor chips is configured to store stackinginformation which defines its own stacked position, and the through-holevia scanning circuit is configured to allow current sources of othersemiconductor chips other than an uppermost semiconductor chip and alowermost semiconductor chip among the plurality of semiconductor chipsto be floating according to the stacking information.